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1 ltc1064-7 10647fb linear phase, 8th order lowpass filter steeper roll-off than 8th order bessel filters f cutoff up to 100khz phase equalized filter in 14-pin package phase and group delay response fully tested transient response exhibits 5% overshoot andno ringing wide dynamic range 72db thd or better throughout a 50khz passband no external components needed available in 14-pin dip and 16-pin so widepackages the ltc 1064-7 is a clock-tunable monolithic 8th order lowpass filter with linear passband phase and flat groupdelay. the amplitude response approximates a maximally flat passband while it exhibits steeper roll-off than an equivalent 8th order bessel filter. for instance, at twice the cutoff frequency the filter attains 34db attenuation (vs 12db for bessel), while at three times the cutoff frequency, the filter attains 68db attenuation (vs 30db for bessel). the cutoff frequency of the ltc1064-7 is tuned via an external ttl or cmos clock. the ltc1064-7 features wide dynamic range. with single 5v supply, the s/n + thd is 76db. optimum 92db s/n is obtained with 7.5v supplies. the clock-to-cutoff frequency ratio of the ltc1064-7 canbe set to 50:1 (pin 10 to v + ) or 100:1 (pin 10 to v ). when the filter operates at clock-to-cutoff frequency ratioof 50:1, the input is double-sampled to lower the risk of aliasing. the ltc1064-7 is pin-compatible with the ltc1064-x series, ltc1164-7 and ltc1264-7. data communication filters time delay networks phase-matched filters 80khz linear phase lowpass filter eye diagram 12 3 4 5 6 7 1413 12 11 10 98 ltc1064-7 v in 7.5v 7.5v clk = 4mhz 7.5v v out note: the power supplies should be bypassed by a0.1 f capacitor close to the package and any printed circuit board assembly should maintain a distanceof at least 0.2 inches between any output or input pin and the f clk line. 1064-7 ta01 1v/div 1064-7 ta02 1 s/div v s = 7.5v f clk = 4mhz ratio = 50:1 , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. features descriptio u applicatio s u typical applicatio u downloaded from: http:///
2 ltc1064-7 10647fb a u g w a w u w a r b s o lu t ex i t i s total supply voltage (v + to v ) .......................... 16.5v power dissipation ............................................. 400mw burn-in voltage ................................................... 16.5v voltage at any input ..... (v ?0.3v) v in (v + + 0.3v) storage temperature range ................ 65 c to 150 c operating temperature range ltc1064-7c ....................................... 40 c to 85 c ltc1064-7m obsolete .............. ?5 c to 125 c lead temperature (soldering, 10 sec)................. 300 c e lectr ic al c c hara terist ics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c.v s = 7.5v, r l = 10k, t a = 25 c, f cutoff = 10khz or 20khz, f clk = 1mhz, ttl or cmos level (maximum clock rise and fall time 1 s) and all gain measurements are referenced to passband gain, unless otherwise specified. the filter cutoff frequency is abbreviated as f cutoff or f c . parameter conditions min typ max units passband gain 0.1hz f 0.25 f cutoff f test = 5khz, (f clk /f c ) = 50:1 0.60 0.10 0.65 db gain at 0.5 f cutoff f test = 10khz, (f clk /f c ) = 50:1 0.90 0.35 0.15 db f test = 5khz, (f clk /f c ) = 100:1 1.30 0.35 1.25 db gain at 0.75 f cutoff f test = 15khz, (f clk /f c ) = 50:1 2.0 ?.0 0.35 db gain at f cutoff f test = 20khz, (f clk /f c ) = 50:1 4.50 3.4 2.50 db f test = 10khz, (f clk /f c ) = 100:1 5.75 4.5 3.75 db gain at 2 f cutoff f test = 40khz, (f clk /f c ) = 50:1 36.5 34.0 31.75 db f test = 20khz, (f clk /f c ) = 100:1 37.0 34.5 31.75 db gain with f clk = 20khz f test = 200hz, (f clk /f c ) = 100:1 6.5 4.3 3.5 db gain with f clk = 400khz, v s = 2.375v f test = 4khz, (f clk /f c ) = 50:1 0.9 0.3 0.25 db f test = 8khz, (f clk /f c ) = 50:1 4.5 3.3 2.00 db phase factor ( f ) 0.1hz f f cutoff phase = 180 ? f (f/f c ) (f clk /f c ) = 50:1 430 2.0 deg (note 2) (f clk /f c ) = 100:1 421 2.5 deg (f clk /f c ) = 50:1 422 430 437 deg (f clk /f c ) = 100:1 414 421 429 deg wu u package / o rder i for atio order part number ltc1064-7cnltc1064-7cj ltc1064-7mj order part number ltc1064-7csw t jmax = 110 c, ja = 85 c/w t jmax = 110 c, ja = 65 c/w (n) top view sw package 16-lead plastic so (wide) 12 3 4 5 6 7 8 1615 14 13 12 11 10 9 nc v in gnd v + gnd nc lp (a) inv (a) r in (a) ncv ncf clk 50/100nc v out (note 1) consult ltc marketing for parts specified with wider operating temperature ranges. order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consider the n package as an alternate source 12 3 4 5 6 7 top view n package 14-lead plastic dip 1413 12 11 10 98 nc v in gnd v + gnd lp (a) inv (a) r in (a) ncv f clk 50/100v out nc t jmax = 150 c, ja = 65 c/w (j) j package 14-lead ceramic dip obsolete package downloaded from: http:///
3 ltc1064-7 10647fb e lectr ic al c c hara terist ics parameter conditions min typ max units phase nonlinearity (f clk /f c ) = 50:1 1.0 % (notes 2, 4) (f clk /f c ) = 100:1 1.0 % (f clk /f c ) = 50:1 2.0 % (f clk /f c ) = 100:1 2.0 % group delay (t d )( f clk /f c ) = 50:1, f f cutoff 59.7 0.5 s t d = ( f /360)(1/ f c )( f clk /f c ) = 100:1, f f cutoff 117.0 1.0 s (note 3) (f clk /f c ) = 50:1, f f cutoff 58.6 59.7 60.7 s (f clk /f c ) = 100:1, f f cutoff 115.0 117.0 119.0 s group delay deviation (f clk /f c ) = 50:1, f f cutoff 1.0 % (notes 3, 4) (f clk /f c ) = 100:1, f f cutoff 1.0 % (f clk /f c ) = 50:1, f f cutoff 2.0 % (f clk /f c ) = 100:1, f f cutoff 2.0 % input frequency range (table 9) (f clk /f c ) = 50:1 4 ltc1064-7 10647fb figure 1. phase response in the passband (note 2) frequency (khz) 0 360 phase (deg) 270 180 ?0 0 90 180 4 8 12 16 1164-7 f01 20 2 6 10 14 18 f clk = 1mhz ratio = 50:1 note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired.note 2: input frequencies, f, are linearly phase shifted through the filter as long as f f c ; f c = cutoff frequency. figure 1 curve shows the typical phase response of an ltc1064-7operating at f clk = 1mhz, ratio = 50:1, f c = 20khz and it closely matches an ideal straight line. the phase shift is described by: phase shift =180 ? f (f/f c ); f f c . f is arbitrarily called the ?hase factor?expressed in degrees. the phase factor allows the calculation of the phase at a given frequency.example: the phase shift at 14khz of the ltc1064-7 shown in figure 1 is: phase shift = 180 ?430 (14khz/20khz) nonlinearity = ?21 1% or ?21 1.20 . note 3: group delay and group delay deviation are calculated from the measured phase factor and phase deviation specifications.note 4: phase deviation and group delay deviation for ltc1064-7mj is 4%. note 5: the ac swing is typically 11v p-p , 7v p-p , 2.8v p-p , with 7.5v, 5v, 2.5v supply respectively. for more information refer to the thd + noise vs input graphs. electrical characteristics downloaded from: http:///
5 ltc1064-7 10647fb cc hara terist ics uw a t y p i ca lper f o r c e phase factor vs f clk (typical unit) passband gain and phase gain vs frequency phase factor vs f clk (min and max representative units) phase factor vs f clk (min and max representative units)passband gain and phase frequency (khz) 0.1 ?0 gain (db) ?0 ?0 ?0 ?0 1 10 100 1064-7 g01 ?0 ?0 ?0 0 ?0 10 ?00?10 50:1 100:1 v s = 5v f clk = 1mhz t a = 25? f clk (mhz) 0.5 435 phase factor 425 455 465 485 1064-7 g02 445 475 2.0 3.5 1.0 2.5 3.0 415 1.5 v s = 5v (f clk /f c ) = 50:1 70? 25? 0? f clk (mhz) 0.5 435 phase factor 425 455 465 485 1064-7 g03 445 475 2.0 3.5 1.0 2.5 3.0 415 1.5 25? 70? 0? v s = 5v (f clk /f c ) = 100:1 phase factor vs f clk (typical unit) f clk (mhz) 0.5 435 phase factor 430 440 1064-7 g05 445 2.0 1.5 420 1.0 425 v s = 5v t a = 25? pins 3, 5 at 2v(f clk /f c ) = 50:1 f clk (mhz) 0.5 435 phase factor 430 440 1064-7 g04 445 2.0 3.5 1.0 2.5 3.0 420 1.5 v s = 5v t a = 25? (f clk /f c ) = 50:1 425 frequency (khz) 4 gain (db) ? 0 20 1064-7 g06 ? ? 6 12 16 phase (deg) 2 32 1 ? ?? 180120 60 0 ?0 120 ?80 240 300 360 81 01 41 82 2 v s = ?v f clk = 1mhz (f clk /f c ) = 50:1 phase gain frequency (khz) 4 gain (db) ? 0 20 1064-7 g07 ? ? 6 12 16 phase (deg) 2 32 1 ? ?? 180120 60 0 ?0 120 ?80 240 300 360 81 01 41 82 2 v s = ?v f clk = 2mhz (f clk /f c ) = 100:1 phase gain downloaded from: http:///
6 ltc1064-7 10647fb thd + noise vs frequency delay vs frequency and f clk cc hara terist ics uw a t y p i ca lper f o r c e delay vs frequency and f clk thd + noise vs frequency frequency (khz) 1 0 delay ( s) 50 100 150 200 250 61 6 2 1 1064-7 g14 36 11 26 31 a d b c v s = 5v t a = 25? (f clk /f c ) = 100:1 a. f clk = 0.5mhz b. f clk = 1.5mhz c. f clk = 2.5mhz d. f clk = 3.5mhz frequency (khz) 1 ?0 thd + noise (db) ?0 ?0 ?0 ?0 10 1064-7 g15 ?5 ?5 ?5 ?5 ?5 v s = 7.5v v in = 2v rms f clk = 1mhz (f clk /f c ) = 50:1 (100k resistorpin 9 to v ) ?0 20 frequency (khz) 11 0 5 0 1064-7 g16 ?0 thd + noise (db) ?0 ?0 ?0 ?5 ?5 ?0 ?5 ?0 ?5 ?5 v s = 7.5v v in = 1v rms f clk = 2.5mhz (f clk /f c ) = 50:1 (100k resistorpin 9 to v ) frequency (khz) 2 0 delay ( s) 25 50 75 100 125 12 32 42 1064-7 g13 72 22 52 62 a d b c v s = 5v t a = 25? (f clk /f c ) = 50:1 a. f clk = 0.5mhz b. f clk = 1.5mhz c. f clk = 2.5mhz d. f clk = 3.5mhz frequency (khz) 1 ? gain (db) ? ? 1 3 10 100 1064-7 g12 ? ? 0 2 4 v s = single 5v (f clk /f c ) = 50:1 5 a. f clk = 0.5mhz b. f clk = 1.0mhz c. f clk = 1.5mhz d. f clk = 2.0mhz d a b c frequency (khz) 1 ? gain (db) ? ? 1 3 10 100 1064-7 g11 ? ? 0 2 4 v s = single 5v t a = 25? (f clk /f c ) = 50:1 5 a. f clk = 0.5mhz b. f clk = 1.0mhz c. f clk = 1.5mhz d. f clk = 2.0mhz d c a b frequency (khz) 10 ? gain (db) ? ? 1 3 100 1000 1064-7 g08 ? ? 0 2 4 e 5 10 c a d a. f clk = 1mhz b. f clk = 2mhz c. f clk = 3mhz d. f clk = 4mhz e. f clk = 5mhz v s = 7.5v t a = 25? (f clk /f c ) = 50:1 b frequency (khz) 1 ? gain (db) ? ? 1 3 100 1000 1064-7 g09 ? ? 0 2 4 e 5 10 c a d a. f clk = 1mhz b. f clk = 2mhz c. f clk = 3mhz d. f clk = 4mhz e. f clk = 5mhz v s = 7.5v (f clk /f c ) = 50:1 b frequency (khz) 1 ? gain (db) ? ? 1 3 10 100 1064-7 g10 ? ? 0 2 4 v s = ?v (f clk /f c ) = 50:1 5 a. f clk = 0.5mhz b. f clk = 1.5mhz c. f clk = 2.5mhz d. f clk = 3.5mhz d c a b passband gain vs frequencyand f clk passband gain vs frequency andf clk at t a = 85 c passband gain vs frequency andf clk at t a = 85 c passband gain vs frequency andf clk at t a = 85 c passband gain vs frequencyand f clk downloaded from: http:///
7 ltc1064-7 10647fb cc hara terist ics uw a t y p i ca lper f o r c e thd + noise vs frequency thd + noise vs input phase matching vs frequency total power supply voltage (v) 0 power supply current (ma) 4844 40 36 32 28 24 20 16 12 84 0 2 6 12 16 1064-7 g25 20 4 8 10 14 18 22 24 55? 25? 125? f clk = 1mhz frequency (f cutoff /frequency) 0 phase difference (deg) 3 4 5 0.8 1064-7 g24 2 1 0 0.2 0.4 0.6 1.0 phase difference betweenany two units (sample of 50 representative units) v s ?v f clk 2.5mhz (f clk /f c ) = 50:1 or 100:1 t a = 0? to 70? input (v rms ) 0.1 ?0 thd + noise (db) ?0 ?0 ?0 ?0 1 1064-7 g23 ?5 ?5 ?5 ?5 ?5 v s = single 5v f in = 1khz f clk = 500khz (f clk /f c ) = 100:1 ?0 2 b a. pins 3, 5 at 2vb. pins 3, 5 at 2.5v a input (v rms ) 0.1 1 5 1064-7 g20 ?0 thd + noise (db) ?0 ?0 ?0 ?5 ?5 ?0 ?5 ?0 ?5 ?5 f in = 1khz f clk = 1mhz (f clk /f c ) = 50:1 (100k pin 9to v ) a b a. v s = 5v b. v s = 7.5v input (v rms ) 0.1 1 5 1064-7 g21 ?0 thd + noise (db) ?0 ?0 ?0 ?5 ?5 ?0 ?5 ?0 ?5 ?5 f in = 1khz f clk = 2mhz (f clk /f c ) = 100:1 a b a. v s = 5v b. v s = 7.5v input (v rms ) 0.1 ?0 thd + noise (db) ?0 ?0 ?0 ?0 1 1064-7 g22 ?5 ?5 ?5 ?5 ?5 v s = single 5v f in = 1khz f clk = 1mhz (f clk /f c ) = 50:1 ?0 2 b a. pins 3, 5 at 2vb. pins 3, 5 at 2.5v a thd + noise vs input thd + noise vs input thd + noise vs input power supply current vspower supply voltage thd + noise vs frequency thd + noise vs frequency frequency (khz) 1 ?0 thd + noise (db) ?0 ?0 ?0 ?0 10 1064-7 g17 ?5 ?5 ?5 ?5 ?5 v s = ?v v in = 1v rms f clk = 1mhz (f clk /f c ) = 50:1 (100k resistorpin 9 to v ) ?0 20 frequency (khz) 1 ?0 thd + noise (db) ?0 ?0 ?0 ?0 10 1064-7 g18 ?5 ?5 ?5 ?5 ?5 v s = single 5v v in = 0.5v rms f clk = 1mhz (f clk /f c ) = 50:1 (pins 3, 5 at 2v) ?0 20 frequency (khz) 1 thd + noise (db) 25 1064-7 g19 34 ?0 ?0 ?5 ?5 ?5 ?5 ?0 ?0 ?0 ?0 ?5 v s = single 5v v in = 0.5v rms f clk = 500khz (f clk /f c ) = 100:1 (pins 3, 5 at 2v) downloaded from: http:///
8 ltc1064-7 10647fb cc hara terist ics uw a t y p i ca lper f o r c e table 2. passband gain and phasev s = 7.5v, (f clk /f c ) = 100:1, t a = 25 c frequency (khz) gain (db) phase (deg) f clk = 1mhz (typical unit) 0.000 0.203 180.00 2.500 0.203 74.07 5.000 0.741 31.71 7.500 1.831 136.47 10.000 4.451 240.17 f clk = 2mhz (typical unit) 0.000 0.152 180.00 5.000 0.152 73.79 10.000 0.575 32.47 15.000 1.501 138.11 20.000 3.973 243.84 f clk = 3mhz (typical unit) 0.000 0.123 180.00 7.500 0.123 73.32 15.000 0.481 33.64 22.500 1.312 140.14 30.000 3.654 247.11 table 1. passband gain and phasev s = 7.5v, (f clk /f c ) = 50:1, t a = 25 c frequency (khz) gain (db) phase (deg) f clk = 1mhz (typical unit) 0.000 0.086 180.00 5.000 0.086 73.54 10.000 0.334 33.60 15.000 1.051 140.81 20.000 3.316 249.30 f clk = 2mhz (typical unit) 0.000 0.131 180.00 10.000 0.131 72.88 20.000 0.442 34.71 30.000 1.108 141.99 40.000 3.115 250.45 f clk = 3mhz (typical unit) 0.000 0.156 180.00 15.000 0.156 72.54 30.000 0.459 35.01 45.000 0.941 141.95 60.000 2.508 250.53 f clk = 4mhz (typical unit) 0.000 0.121 180.00 20.000 0.121 72.12 40.000 0.292 35.75 60.000 0.476 142.92 80.000 1.539 252.63 f clk = 5mhz (typical unit) 0.000 0.045 180.00 25.000 0.045 70.85 50.000 0.006 38.25 75.000 0.185 146.77 100.000 0.356 259.27 frequency (khz) gain (db) phase (deg) f clk = 4mhz (typical unit) 0.000 0.116 180.00 10.000 0.116 72.49 20.000 0.436 35.21 30.000 1.171 142.33 40.000 3.353 250.12 f clk = 5mhz (typical unit) 0.000 0.097 180.00 12.500 0.097 71.00 25.000 0.351 38.08 37.500 0.951 146.51 50.000 2.999 256.13 table 3. passband gain and phasev s = 5v, (f clk /f c ) = 50:1, t a = 25 c frequency (khz) gain (db) phase (deg) f clk = 0.5mhz (typical unit) 0.000 0.081 180.00 2.500 0.081 73.71 5.000 0.345 33.31 7.500 1.063 140.36 10.000 3.283 248.52 f clk = 1mhz (typical unit) 0.000 0.071 180.00 5.000 0.071 73.44 10.000 0.322 33.83 15.000 1.036 141.13 20.000 3.284 249.68 f clk = 1.5mhz (typical unit) 0.000 0.095 180.00 7.500 0.095 73.03 15.000 0.392 34.53 22.500 1.075 141.89 30.000 3.155 250.45 f clk = 2mhz (typical unit) 0.000 0.127 180.00 10.000 0.127 72.81 20.000 0.447 34.70 30.000 1.041 141.77 40.000 2.856 250.24 f clk = 2.5mhz (typical unit) 0.000 0.126 180.00 12.500 0.126 72.61 25.000 0.411 34.91 37.500 0.864 141.88 50.000 2.397 250.62 f clk = 3mhz (typical unit) 0.000 0.102 180.00 15.000 0.102 72.23 30.000 0.292 35.64 45.000 0.546 142.96 60.000 1.769 252.73 downloaded from: http:///
9 ltc1064-7 10647fb cc hara terist ics uw a t y p i ca lper f o r c e table 5. passband gain and phasev s = single 5v, (f clk /f c ) = 50:1, t a = 25 c frequency (khz) gain (db) phase (deg) f clk = 0.5mhz (typical unit) 0.000 0.134 180.00 2.500 0.134 73.52 5.000 0.391 33.67 7.500 1.109 140.92 10.000 3.351 249.32 f clk = 1mhz (typical unit) 0.000 0.148 180.00 5.000 0.148 73.07 10.000 0.423 34.63 15.000 1.111 142.25 20.000 3.241 251.03 f clk = 1.5mhz (typical unit) 0.000 0.157 180.00 7.500 0.157 72.73 15.000 0.456 34.83 22.500 0.981 142.08 30.000 2.687 251.09 f clk = 2mhz (typical unit) 0.000 0.188 180.00 10.000 0.188 71.37 20.000 0.304 37.52 30.000 0.513 146.11 40.000 1.824 257.46 table 4. passband gain and phasev s = 5v, (f clk /f c ) = 100:1, t a = 25 c frequency (khz) gain (db) phase (deg) f clk = 0.5mhz (typical unit) 0.000 0.186 180.00 1.250 0.186 74.10 2.500 0.726 31.65 3.750 1.805 136.48 5.000 4.402 240.33 f clk = 1mhz (typical unit) 0.000 0.184 180.00 2.500 0.184 74.02 5.000 0.712 31.80 7.500 1.785 136.61 10.000 4.387 240.43 f clk = 1.5mhz (typical unit) 0.000 0.145 180.00 3.750 0.145 73.84 7.500 0.596 32.32 11.250 1.556 137.73 15.000 4.047 242.95 f clk = 2mhz (typical unit) 0.000 0.116 180.00 5.000 0.116 73.64 10.000 0.494 32.93 15.000 1.361 139.03 20.000 3.761 245.57 f clk = 2.5mhz (typical unit) 0.000 0.101 180.00 6.250 0.101 73.17 12.500 0.452 33.93 18.750 1.273 140.58 25.000 3.611 247.80 f clk = 3mhz (typical unit) 0.000 0.105 180.00 7.500 0.105 72.36 15.000 0.445 35.47 22.500 1.228 142.70 30.000 3.509 250.58 f clk = 3.5mhzmhz (typical unit) 0.000 0.104 180.00 8.750 0.104 70.81 17.500 0.437 38.39 26.250 1.188 146.85 35.000 3.478 256.10 table 3. passband gain and phasev s = 5v, (f clk /f c ) = 50:1, t a = 25 c frequency (khz) gain (db) phase (deg) f clk = 3.5mhz (typical unit) 0.000 0.054 180.00 17.500 0.054 71.07 35.000 0.108 38.00 52.500 0.137 146.68 70.000 1.104 258.97 table 6. passband gain and phasev s = single 5v, (f clk /f c ) = 100:1, t a = 25 c frequency (khz) gain (db) phase (deg) f clk = 0.5mhz (typical unit) 0.000 0.243 180.00 1.250 0.243 73.91 2.500 0.776 31.98 3.750 1.861 136.98 5.000 4.483 240.90 f clk = 1mhz (typical unit) 0.000 0.208 180.00 2.500 0.208 73.76 5.000 0.678 32.47 7.500 1.679 137.87 10.000 4.221 242.65 f clk = 1.5mhz (typical unit) 0.000 0.115 180.00 3.750 0.115 73.26 7.500 0.473 33.73 11.250 1.314 140.40 15.000 3.715 247.66 f clk = 2mhz (typical unit) 0.000 0.209 180.00 5.000 0.209 71.18 10.000 0.499 37.85 15.000 1.281 146.27 20.000 3.695 255.38 downloaded from: http:///
10 ltc1064-7 10647fb pi fu ctio s u uu power supply pins (4, 12)the v + (pin 4) and the v (pin 12) should be bypassed with a 0.1 f capacitor to an adequate analog ground. the filter? power supplies should be isolated from otherdigital or high voltage analog supplies. a low noise linear supply is recommended. using a switching power supply will lower the signal-to-noise ratio of the filter. the supply during power-up should have a slew rate less than 1v/ s. when v + is applied before v and v is allowed to go above ground, a signal diode should clamp v ? to prevent latch-up. figures 2 and 3 show typical connections fordual and single supply operation. figure 2. dual supply operation for an f clk /f cutoff = 50:1 figure 3. single supply operation for an f clk /f cutoff = 50:1 clock input pin (11)any ttl or cmos clock source with a square-wave output and 50% duty cycle ( 10%) is an adequate clock source for the device. the power supply for the clock sourceshould not be the filter? power supply. the analog ground for the filter should be connected to clock? ground at asingle point only. table 7 shows the clock? low and high level threshold values for a dual or single supply operation. a pulse generator can be used as a clock source provided the high level on time is greater than 0.1 s. sine waves are not recommended for clock input frequencies less than100khz, since excessively slow clock rise or fall times generate internal clock jitter (maximum clock rise or fall time 1 s). the clock signal should be routed from the right side of the ic package and perpendicular to it to avoidcoupling to any input or output analog signal path. a 200 ? resistor between clock source and pin 11 will slow downthe rise and fall times of the clock to further reduce charge coupling (figures 2 and 3). table 7. clock source high and low threshold levels power supply high level low level dual supply = 7.5v 2.18v 0.5v dual supply = 5v 1.45v 0.5v dual supply = 2.5v 0.73v 2.0v single supply = 12v 7.80v 6.5v single suppl = 5v 1.45v 0.5v analog ground pins (3, 5)the filter performance depends on the quality of the analog signal ground. for either dual or single supply operation, an analog ground plane surrounding the pack- age is recommended. the analog ground plane should be connected to any digital ground at a single point. for dual supply operation, pin 3 should be connected to the analog ground plane. for single supply operation pin 3 should be biased at 1/2 supply and should be bypassed to the analog ground plane with at least a 1 f capacitor (figure 3). for single 5v operation at the highest f clk of 2mhz, pin 3 should be biased at 2v. this minimizes passband gain andphase variations. ratio input pin (10) the dc level at this pin determines the ratio of the clock frequency to the cutoff frequency of the filter. pin 10 at v + gives a 50:1 ratio and pin 10 at v gives a 100:1 ratio. for single supply operation the ratio is 50:1 when pin 10 is atv + and 100:1 when pin 10 is at ground. when pin 10 is not tied to ground, it should be bypassed to analog ground 12 3 4 5 6 7 1413 12 11 10 98 v in v + 200 ? v v out ltc1064-7 digital supply + gnd clock source 1064-7 f02 0.1 f 0.1 f v + 12 3 4 5 6 7 1413 12 11 10 98 v in v + 200 ? v out digital supply + gnd clock source 1064-7 f03 + ltc1064-7 0.1 f 1 f 10k 10k v + downloaded from: http:///
11 ltc1064-7 10647fb pi fu ctio s u uu external connection pins (7, 14)pins 7 and 14 should be connected together. in a printed circuit board the connection should be done under the ic package through a short trace surrounded by the analog ground plane. nc pins (1, 5, 8, 13) pins 1, 5, 8 and 13 are not connected to any internal circuit point on the device and should preferably be tied to analog ground. figure 4. buffer for filter output 1k 1064-7 f04 + lt1220 with a 0.1 f capacitor. if the dc level at pin 10 is switched mechanically or electrically at slew rates greater than1v/ s while the device is operating, a 10k resistor should be connected between pin 10 and the dc source.filter input pin (2) the input pin is connected internally through a 40k resis- tor tied to the inverting input of an op amp. filter output pins (9, 6) pin 9 is the specified output of the filter; it can typically source 3ma and sink 1ma. driving coaxial cables or resistive loads less than 20k will degrade the total har- monic distortion of the filter. when evaluating the device? distortion an output buffer is required. a noninverting buffer, figure 4, can be used provided that its input common mode range is well within the filter? output swing. pin 6 is an intermediate filter output providing an unspecified 6th order lowpass filter. pin 6 should not be loaded. clock feedthroughclock feedthrough is defined as the rms value of the clock frequency and its harmonics that are present at the filter? output pin (9). the clock feedthrough is tested with the input pin (2) grounded and it depends on pc board layout and on the value of the power supplies. with proper layout techniques the values of the clock feedthrough are shown in table 8. table 8. clock feedthrough v s 50:1 100:1 single 5v 90 v rms 100 v rms 5v 100 v rms 300 v rms 7.5v 120 v rms 650 v rms note: the clock feedthrough at single 5v is imbedded in thewideband noise of the filter. clock waveform is a square wave. amplitude strongly depends on scope probing techniquesas well as grounding and power supply bypassing. the clock feedthrough, if bothersome, can be greatly reduced by adding a simple r/c lowpass network at the output of the filter pin (9). this r/c will completely eliminate any switching transients. wideband noise the wideband noise of the filter is the total rms value of the device? noise spectral density and it is used to determine the operating signal-to-noise ratio. most of its frequency contents lie within the filter passband and it cannot be reduced with post filtering. for instance, the ltc1064-7 wideband noise at 5v supply is 105 v rms , 95 v rms of which have frequency contents from dc up to the filter? cutoff frequency. the total wideband noise( v rms ) is nearly independent of the value of the clock. the clock feedthrough specifications are not part of thewideband noise. any parasitic switching transients during the rise and falledges of the incoming clock are not part of the clock feedthrough specifications. switching transients have fre- quency contents much higher than the applied clock; their u s a o pp l ic at i wu u i for atio downloaded from: http:///
12 ltc1064-7 10647fb u s a o pp l ic at i wu u i for atio speed limitationsto avoid op amp slew rate limiting at maximum clock frequencies, the signal amplitude should be kept below a specified level as shown in table 9. table 9. maximum v in vs v s and clock power supply maximum f clk maximum v in 7.5v 5.0mhz 1.8v rms (f in > 80khz) 4.5mhz 2.3v rms (f in > 80khz) 4.0mhz 2.7v rms (f in > 80khz) 3.5mhz 1.4v rms (f in > 500khz) 5v 3.5mhz 1.6v rms (f in > 80khz) 3.0mhz 0.7v rms (f in > 400khz) single 5v 2.0mhz 0.5v rms (f in > 250khz) table 10. transient response of ltc lowpass filters delay rise settling over- time* time** time*** shoot lowpass filter (sec) (sec) (sec) (%) ltc1064-3 bessel 0.50/f c 0.34/f c 0.80/f c 0.5 ltc1164-5 bessel 0.43/f c 0.34/f c 0.85/f c 0 ltc1164-6 bessel 0.43/f c 0.34/f c 1.15/f c 1 ltc1264-7 linear phase 1.15/f c 0.36/f c 2.05/f c 5 ltc1164-7 linear phase 1.20/f c 0.39/f c 2.2/f c 5 ltc1064-7 linear phase 1.20/f c 0.39/f c 2.2/f c 5 ltc1164-5 butterworth 0.80/f c 0.48/f c 2.4/f c 11 ltc1164-6 elliptic 0.85/f c 0.54/f c 4.3/f c 18 ltc1064-4 elliptic 0.90/f c 0.54/f c 4.5/f c 20 ltc1064-1 elliptic 0.85/f c 0.54/f c 6.5/f c 20 * to 50% 5%, ** 10% to 90% 5%, *** to 1% 0.5% table 11. aliasing (f clk = 100khz) input frequency output level output frequency (v in = 1v rms , (relative to input, (aliased frequency f in = f clk f out ) 0db = 1v rms )f out = abs [f clk f in ]) (khz) (db) (khz) 50:1, f cutoff = 2khz 190 (or 210) 76.1 10.0 195 (or 205) 51.9 5.0 196 (or 204) 36.3 4.0 197 (or 203) 18.4 3.0 198 (or 202) 3.0 2.0 199.5 (or 200.5) 0.2 0.5 100:1, f cutoff = 1khz 97 (or 103) ?4.2 3.0 97.5 (or 102.5) 53.2 2.5 98 (or 102) 36.9 2.0 98.5 (or 101.5) 19.6 1.5 99 (or 101) 5.2 1.0 99.5 (or 100.5) 0.7 0.5 transient response 2v/div 50 s/div 1064-7 f05 v s = 7.5v, f in = 2khz 3v f clk = 1mhz, ratio = 50:1 figure 6. input 90% 50% 10% output t r t d t s 1064-7 f06 rise time (t r ) = 5% 0.39 f cutoff settling time (t s ) = 5% (to 1% of output) 2.2 f cutoff delay time (t d ) = group delay (to 50% of output) 1.2 f cutoff figure 5. aliasingaliasing is an inherent phenomenon of sampled data systems and it occurs when input frequencies close to the sampling frequency are applied. for the ltc1064-7 case at 100:1, an input signal whose frequency is in the range of f clk 3%, will be aliased back into the filter? passband. if, for instance, an ltc1064-7 operating with a 100khzclock and 1khz cutoff frequency receives a 98khz, 10mv input signal, a 2khz, 143 v rms alias signal will appear at its output. when the ltc1064-7 operates with a clock-to-cutoff frequency of 50:1, aliasing occurs at twice the clock frequency. table 11 shows details. downloaded from: http:///
13 ltc1064-7 10647fb obsolete package j package 14-lead cerdip (narrow .300 inch, hermetic) (reference ltc dwg # 05-08-1110) u package descriptio j14 0801 .045 ?.065 (1.143 ?1.651) .100 (2.54) bsc .014 ?.026 (0.360 ?0.660) .200 (5.080) max .015 ?.060 (0.381 ?1.524) .125 (3.175) min .300 bsc (7.62 bsc) .008 ?.018 (0.203 ?0.457) 0 ?15 1 234 56 7 .220 ?.310 (5.588 ?7.874) .785 (19.939) max .005 (0.127) min 14 11 8 9 10 13 12 .025 (0.635) rad typ note: lead dimensions apply to solder dip/plate or tin plate leads downloaded from: http:///
14 ltc1064-7 10647fb n14 1103 .020 (0.508) min .120 (3.048) min .130 .005 (3.302 0.127) .045 ?.065 (1.143 ?1.651) .065 (1.651) typ .018 .003 (0.457 0.076) .005 (0.127) min .255 .015* (6.477 0.381) .770* (19.558) max 3 1 2 4 5 6 7 8 9 10 11 12 13 14 .008 ?.015 (0.203 ?0.381) .300 ?.325 (7.620 ?8.255) .325 +.035?015 +0.889 0.381 8.255 () note:1. dimensions are inches millimeters *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 inch (0.254mm) .100 (2.54) bsc n package 14-lead pdip (narrow .300 inch) (reference ltc dwg # 05-08-1510) u package descriptio downloaded from: http:///
15 ltc1064-7 10647fb s16 (wide) 0502 note 3 .398 ?.413 (10.109 ?10.490) note 4 16 15 14 13 12 11 10 9 1 n 23 4 5 6 78 n/2 .394 ?.419 (10.007 ?10.643) .037 ?.045 (0.940 ?1.143) .004 ?.012 (0.102 ?0.305) .093 ?.104 (2.362 ?2.642) .050 (1.270) bsc .014 ?.019 (0.356 ?0.482) typ 0 ?8 typ note 3 .009 ?.013 (0.229 ?0.330) .005 (0.127) rad min .016 ?.050 (0.406 ?1.270) .291 ?.299 (7.391 ?7.595) note 4 45 .010 ?.029 (0.254 ?0.737) inches (millimeters) note:1. dimensions in 2. drawing not to scale 3. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options 4. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) .420 min .325 .005 recommended solder pad layout .045 .005 n 1 2 3 n/2 .050 bsc .030 .005 typ sw package 16-lead plastic small outline (wide .300 inch) (reference ltc dwg # 05-08-1620) u package descriptio information furnished by linear technology corporation is believed to be accurate and reliable.however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. downloaded from: http:///
16 ltc1064-7 10647fb related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 1992 lt/lt 0905 rev b printed in usa part number description comments ltc1064 universal filter building block allows for bandpass (up to 50khz) using external resistors ltc1064-1/2/3/4 8th order low pass filters, f o max = 100khz elliptic, butterworth, bessel, cauer ltc1164 universal filter building block allows for bandpass (up to 20khz) using external resistors ltc1164-5/6/7 8th order low pass filters, f o max = 20khz butterworth, bessel or elliptic ltc1264 universal filter building block allows for bandpass (up to 100khz) using external resistors ltc1264-7 8th order low pass filter, f o max = 200khz flat group delay, high speed lowpass filter lt6600-2.5 low noise differential amp and 10mhz lowpass 55 v rms noise 100khz to 10mhz 3v supply lt6600-10 low noise differential amp and 20mhz lowpass 86 v rms noise 100khz to 20mhz 3v supply 12 3 4 5 6 7 1413 12 11 10 98 ltc1064-7 v in 7.5v 7.5v clk = 4mhz 7.5v v out note: the power supplies should be bypassed by a0.1 f capacitor close to the package and any printed circuit board assembly should maintain a distanceof at least 0.2 inches between any output or input pin and the f clk line. 1064-7 ta01 80khz linear phase lowpass filter eye diagram 1v/div 1064-7 ta02 1 s/div v s = 7.5v f clk = 4mhz ratio = 50:1 u typical applicatio downloaded from: http:///

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